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DS1780 cpu peripheral monitor DS1780 072898 1/28 features ? directtodigital temperature sensor requires no external components or user calibration ? two fan speed sensors ? monitors 6 power supply voltages ? 8bit dac for fan speed control ? intrusion detect for security (detects when chassis lid has been removed, even if power is off) ? remote system reset ? system interrupt availability on all monitored func- tions (temperature, voltages, fan speed, chassis intrusion) ? 2wire interface with 2bit addressability ? integrated nand tree for board level testability ? wide power supply range (2.8v v dd 5.75v) ? high integration in a small 24pin 173 mil tssop ? applications include monitoring of personal comput- ers or any microprocessorbased system pin assignment vid0 vid1 vid2 vid3 vid4 +v ccp1 +2.5 v in +3.3 v in +5 v in +12 v in a0/nt out a1 sda scl fan1 fan2 chs gndd v dd int 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 +2.5 v s /+v ccp2 gnda 11 12 13 14 v out /nt in rst DS1780e 24pin tssop (173 mil) pin description a0/nt out address input / nand tree output a1 address input sda 2wire serial data input/output scl 2wire serial clock fanx tachometer inputs chs chassis intrusion detector input gndd digital ground vdd power supply voltage (2.8v to 5.75v) int hardware interrupt output v out /nt in dac output / nand tree input rst remote system reset gnda analog ground +xxv in positive voltage inputs +2.5vs/+vccp2 positive/negative voltage input vidx processor voltage supply readout inputs description the DS1780 is a highly integrated system instrumenta- tion monitor ideal for use in personal computers, or any microprocessorbased system. it monitors ambient temperature, six power supply voltages, and the speed of two fans. fan speed can also be controlled with the use of an internal 8bit dac. all measurements are internally converted to a digital format for easy proces- sing by the cpu. the DS1780 can be reset to its default power up state via a remote reset function with internal debounce and delay. it features an interrupt that can be programmed to become active should any of the functions the DS1780 is monitoring fall out of spec.
DS1780 072898 2/28 for board level testability, an internal nand tree func- tion simplifies the system design. a chassis intrusion input is featured to enhance system security. programming and data readout are accessed via a sim- ple 2wire interface with twobit addressability. the DS1780 power supply range of 2.8v to 5.75v allows for monitoring of parameters for 3v or 5v systems. the DS1780 is assembled in a compact 173 mil tssop package. detailed pin description table 1. pin signal direction description 1 a0/nt out digital i/o the lowest order programmable bit of the 2wire bus address. this pin functions as an output when doing a nand tree test. 2 a1 digital input the highest order programmable bit of the 2wire bus address. 3 sda digital i/o 2wire bus bidirectional data. opendrain output. 4 scl digital input 2wire bus synchronous clock. 5 fan1 digital input 0 to v dd amplitude fan tachometer input. 6 fan2 digital input 0 to v dd amplitude fan tachometer input. 7 chs digital i/o an active high input from an external circuit, which latches a chassis intrusion event. this line can go high without any clamping action regardless of the powered state of the DS1780. the DS1780 pro- vides an internal open drain on this line, controlled by bit 6 of configu- ration register, to provide a minimum 20 ms reset of this signal. 8 gndd ground internally connected to all digital circuitry. 9 v dd power +3.3v or +5v v dd power. bypass with the parallel combination of 10 m f (electrolytic or tantalum) and 0.1 m f (ceramic) bypass capacitors. 10 int digital output activelow programmable interrupt output. the output is enabled when bit 1 of the configuration register is set to 1. the default state is disabled. 11 v out /nt in digital input/ analog output an activehigh input that enables nand tree boardlevel connectiv- ity testing. refer to anand tree testingo section. used as dac out- put when nand tree is not selected. 12 rst digital i/o master reset, 5 ma opendrain driver, active low output with at least a 20 ms minimum pulse width. available when enabled via bit 4 in configuration register. this is a bidirectional i/o pin. it acts as power on reset input. 13 gnda ground internally connected to all analog circuitry. the ground reference for all analog inputs. 14 +2.5v s /+v ccp2 analog input analog input for monitoring 12v or +vccp2. DS1780 will measure voltages on this pin from 0v to 3.6v. an external resistor ladder is required for monitoring a 12v supply (see figure 1). 1519 +xxv in analog inputs a/d inputs for 5 positive voltages. 2024 vidx digital inputs voltage supply readouts from the processor. these values are read in the vid and vid4 status registers.
DS1780 072898 3/28 overview a block diagram of the DS1780 is shown in figure 1. the DS1780 provides 6 analog inputs, an analog out- put, 5 digital inputs, 2 fan speed inputs, a temperature sensor, and interrupt registers on a single chip, which communicates on a 2wire serial bus. the DS1780 per- forms power supply, temperature, and fan monitoring for personal computers. the analog voltages are divided internally by the DS1780. the inputs are then converted to 8bit digital words. the analog inputs are intended to be connected to the several power supplies present in a typical com- puter. temperature can be converted to an 9bit two's complement digital word with a 0.5 c lsb. the analog output is approximately a 01.25v output from an 8bit d/a converter, which is used to control fan speeds. fan inputs measure the period of tachometer pulses from the fans, providing a higher count for lower fan speeds. the fan inputs are digital inputs with an accept- able range of 0 to v dd volts and a transition level of approximately 1.4 volts. fullscale fan counts are 255 (8bit counter) and this represents a stopped or very slow fan. nominal speeds, based on a count of 153, are programmable from 1100 to 8800 rpm on fan1 and fan2. signal conditioning circuitry is included to accommodate slow rise and fall times. the DS1780 provides a number of internal registers, as detailed in table 1. these include: configuration register: provides control and config- uration, as well as initialization. interrupt (int ) status registers: two registers to pro- vide status of each interrupt limit or interrupt event. interrupt (int ) mask registers: allows masking of individual interrupt sources, as well as separate mask- ing for the hardware interrupt output. temperature configuration register: the lower 2 bits of this register configure the type of temperature interrupt mode to be used. bit 7 reflects the lowest bit of the temperature reading. vid register, vid4 register: bits 03 of the vid regis- ter reflect the status of the vid0vid3 pins, bit 0 of the vid4 register reflect the status of vid4 pin. these are simply input pins not processed in any way. in a multi- processor system, these signals will be multiplexed externally from the various processor sources, with the source being controlled by software. value ram: the monitoring results and limits for tem- perature, voltages, and fan counts are all contained in the value ram. when the DS1780 is started, it cycles through each measurement in sequence, and it continuously loops through the sequence approximately once every second. each measured value is compared to values stored in limit registers. when the measured value vio- lates the programmed limit the DS1780 will set a corre- sponding system management interrupt (smi) in the interrupt status registers. one hardware interrupt line, int , is available to generate an smi. int is fully pro- grammable with masking of each interrupt source, and masking of the output. in addition, the configuration reg- ister has control bits to enable or disable the hardware interrupts. a chs (chassis intrusion) digital input is provided. the chassis intrusion input is designed to accept an active high signal from an external circuit that latches when the case is removed from the computer; this pin is a dual purpose pin which will be driven low by the DS1780 to reset the external circuit.
DS1780 072898 4/28 DS1780 functional block diagram figure 1 +12v address inputs (0v or v dd ) 2.8v 5.75v supply +12v in temperature sensor 8bit a/d converter +5v +5v in +3.3v +3.3v in +2.5v +2.5v in +v ccp1 +v ccp1 12v +2.5v s /v ccp2 +v ccp2 or +v ref r 2 r 1 address & i/o control limit comparators amplifier chassis intrusion detector / latch v dd chassis intrusion sense fan speed counter DS1780 memory device configuration device status limit registers measured value ram to cpu 8bit dac system interrupt system reset and initialization gnd DS1780 chs int rst fan1 fan2 v out sda scl a1 a0 processor voltage supply inputs vid0 vid1 vid2 vid3 vid4 note: r1 and r2 on the 12v resistance ladder should be ratioed such that approximately +2.5v appears at the input pin (i.e., r1=4k w , r2=23.2k w ). if a second processor voltage needs to be monitored (vccp2), leave r2 empty, and make r1 500 w , with vccp2 appearing here. 2wire serial data bus when using the 2wire bus, a write will always consist of the DS1780 2wire slave address, followed by the inter- nal address register byte, then the data byte. the internal address register addresses are listed below in table 2. there are two cases for a read: 1. if the internal address register is known to be at the desired address, simply read the DS1780 with the 2wire slave address, followed by the data byte read from the DS1780. 2. if the internal address register value is unknown, write to the DS1780 with the 2wire slave address, followed by the internal address register byte. then restart the serial communication with a read consisting of the 2wire slave address, followed by the data byte read from the DS1780. the default poweron 2wire slave address for the DS1780 is 01011(a1)(a0) binary, where a0a1 reflects the state of the pins defined by the same names. the address can be changed by writing any desired value to the 2wire serial address register (excluding the 2 lsbs). this communication protocol is depicted in the 2wire timing diagrams of figures 2 and 8.
DS1780 072898 5/28 internal address register map table 2 register DS1780 internal hex address power on value notes configuration register 40h 0000 1000 interrupt (int) status register 1 41h 0000 0000 interrupt (int) status register 2 42h 0000 0000 interrupt (int) mask register 1 43h 0000 0000 interrupt (int) mask register 2 44h 0000 0000 chassis intrusion clear register 46h 0000 0000 bit 7 of this register clears chassis intrusion. the other bits are reserved. vid register 47h 0101 xxxx the lower 4 bits reflect the state of vid0vid3 pins. serial address register 48h 0010 11xy x reflects state of a1 and y reflects a0 state vid4 register 49h 1000 000x bit 0 = vid 4. the rest are reserved. temperature configuration register 4bh 0000 0001 test register 15h 0000 0000 do not alter the contents of the register. analog output 19h 1111 1111 full on value ram 20h3dh company id 3eh 1101 1010 read only stepping 3fh 0000 0001 read only
DS1780 072898 6/28 2wire serial communication with the DS1780 figure 2 set internal address only write to internal address register scl sda scl sda s0 0 w aa p s10 w aa a a p start 2wire slave byte DS1780 ack DS1780 ack internal address byte stop start 2wire slave byte DS1780 ack DS1780 ack internal address stop DS1780 ack data byte 11 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 0 1 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 scl sda n d7 d6 d5 d4 d3 d2 d1 d0 data byte p master nack stop 1 1 byte read from current internal address register scl sda s0 0 rd a np start 2wire slave byte DS1780 ack master internal address byte stop 11 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 nack read from new internal address register scl sda s10 w aa start 2wire slave byte DS1780 ack DS1780 ack internal address DS1780 ack 2wire slave 0 1 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r 0 1 0 1 byte 11 a1 a0 rd a repeated start byte operation poweron applying power to the DS1780 causes a reset of several of the registers. power on conditions of the registers are shown in table 2 above. some registers have indeter- minate power on values, such as the limit and ram reg- isters of the value ram page, and these are not shown in the table. upon power up the adc is inactive. writing limits into the value ram should usually be the first action performed after power up. the rst pin is bi directional. it forces reset at power on, but can also be pulled low to force reset internally. operation resets the DS1780 features four distinct resetting functions. each one has a different effect on register contents and the state of the rst output following the event. each one is explained below: poweron reset on por, all internal logic is reset, and registers are cleared to their default state (see tables 10.x). because value ram is typically the first area programmed upon powerup, it does not have a defined state upon por. also, on por, the rst output will be pulled to an active low state for 20 ms (minimum). a por occurs every time v dd crosses the voltage level approximately equivalent to the sum of one nchannel threshold (v tn ) and one pchannel threshold (v tp ), on a powerup or powerdown condition. DS1780 sram contents get ascrambledo when v dd falls below
DS1780 072898 7/28 the greater of one nchannel v t or one pchannel v t . therefore, sram contents will always be in a defined state as supply voltage reaches the minimum spec level of 2.8v, even in a power supply brownout condition. software reset this condition is generated by writing a a1o to bit 4 of the configuration register. it has no effect on DS1780 register contents. it will however pull the rst output to the active low state for a duration of 20 ms (minimum). when the rst output goes active, this bit in the configuration register will clear itself. a software reset is only possible if bit 7 of the int mask register 2 (0x44h) is set to a1o. device initialization this condition is generated by writing a a1o to bit 7 of the configuration register. it will clear all registers in DS1780 memory to their default state except the value ram (0x20h 0x3dh) and ana- log output (0x19h). these locations will remain unchanged from their state before the initialization. this condition has no effect on the rst ouput. this bit is selfclearing. hardware reset this condition is generated by some external source pulling the rst pin below vin(0) (see dc electrical characteristics). the DS1780 will then force the rst signal to remain in the active low state for >20 ms. it will clear all registers in DS1780 memory to their default state except the value ram (0x20h 0x3dh) and analog output (0x19h). these locations will remain unchanged from their state before the hardware reset. operation configuration register control of the DS1780 is provided through the configu- ration register. the configuration register is used to start and stop the DS1780, enable or disable interrupt output and modes, and provide the initialization function described above. bit 0 of the configuration register controls the monitor- ing loop of the DS1780. setting bit 0 low stops the moni- toring loop and puts the DS1780 into a standby mode. 2wire bus communication is still possible with any reg- ister in the DS1780 during the standby mode, however. additionally, the DS1780 will continue to monitor the rst and chs inputs while in a standby mode. setting bit 0 high starts the monitoring loop. bit 1 of the configuration register enables or disables the int interrupt output. setting bit 1 high enables the int output, setting bit 1 low disables the output. bit 3 of the configuration register is used to clear the int interrupt output when set high. the DS1780 moni- toring function will stop until bit 3 is set low. interrupt sta- tus register contents will not be affected. bit 4 of the configuration register is used to initiate a minimum 20 ms reset signal on the rst output if the pin is configured for the reset mode (via bit 7 of the int mask register 2 0x44h). bit 6 of the configuration register is used to reset the chassis intrusion (chs) output pin when set high. bit 7 of the configuration register is used to start a con- figuration register initialization when taken high, as described in the aoperation resetso section. operation monitoring loop the DS1780 monitoring function is started by doing a write to the configuration register and setting the int_clear (bit 3) low, and start (bit 0) high. at this point the int_enable (bit 1) should be set high to enable interrupts (int). the DS1780 then performs a around robino sampling of the inputs, sampling each approxi- mately once a second, in the order (corresponding to locations in the value ram) shown below in table 3. the results of the sampling and conversions can be found in the value ram (table 10.13) and are available at any time. DS1780 monitoring order table 3 temperature reading analog +2.5 v s /v ccp2 analog +12v analog +5v analog +3.3v analog +2.5v analog +v ccp1 fan1 fan2
DS1780 072898 8/28 if conversions are terminated by either of the methods described in the aoperation configuration regis- tero section, the current aroundrobino loop will be com- pleted and the results stored in ram. monitoring will then terminate. when the monitoring again com- mences, monitoring always starts with the temperature reading. operation temperature data format the DS1780 internally converts measured temperature data to a 2's complement data format (in c). the host can read the last completed temperature conversion at any time by setting the internal address register pointer to location 27h, and reading the 8 bits in the register. the format of the data is shown below in table 4. the msb of the register represents the sign bit of the temper- ature reading. for fahrenheit usage, a lookup table or conversion routine must be used. temperature/data relationships table 4 msb lsb (unit = c) s2 6 2 5 2 4 2 3 2 2 2 1 2 0 temperature digital out- put (binary) digital output (hex) +125 c 0111 1101 7dh +25 c 0001 1001 19h +1 c 0000 0001 01h 0 c 0000 0000 00h 1 c 1111 1111 ffh 25 c 1110 0111 e7h 40 c 1101 1000 d8h operation voltage data format the DS1780 contains inputs for directly monitoring the power supplies typically found in a pc (+12v, 12v, +5v, +3.3v, +2.5v, +vccp). these inputs are scaled internally to a reference source, and converted via an 8bit deltasigma adc (analogtodigital converter), thus allowing for a more accurate means of measure- ment since the voltages are referenced to a known value. since these inputs can be greater than v dd , they are not diode protected to the power rails. in addition, small external series resistors such as 510 w should be put into the lines driving the DS1780 to prevent damaging the traces or power supplies should an accidental short connect two power supplies together. the worse such accident would be connecting 12v to +12v; a total of 24v difference, with the series resistors this would draw a maximum of approximately 24 ma. the internal scaling factor depends upon the particular input. the +12v in , +5v in , +3.3v in , and +2.5v in inputs are internally scaled such that the nominal value of the respective supply corresponds to 3/4 of full range, or a decimal count of 192. the approximate resolution is thus equal to: lsb v nom 4/3 v nom 256 this is depicted below in table 5.
DS1780 072898 9/28 voltage/data relationships for positive only voltage inputs (+12v in , +5v in , +3.3v in , and +2.5v in ) table 5 input pin + 12v in + 5v in + 3.3v in + 2.5v in lsb weighting (mv) 62.5 26.0 17.2 13.0 adc result (base 10) pin voltage (v) pin voltage (v) pin voltage (v) pin voltage (v) 0 0 0 0 0 1 0.063 0.026 0.017 0.013 2 0.125 0.052 0.034 0.026 3 0.188 0.078 0.052 0.039 4 0.25 0.104 0.069 0.052 190 11.875 4.948 3.266 2.474 191 11.938 4.974 3.283 2.487 192 12.0 5.0 3.3 2.5 193 12.063 5.026 3.317 2.513 252 15.75 6.563 4.331 3.281 253 15.813 6.589 4.348 3.294 254 15.875 6.615 4.366 3.307 255 15.938 6.641 4.383 3.32 the other two voltage inputs use a slightly different scal- ing technique, due to the nature of the pc voltage they are monitoring. because processor voltage (v ccp ) can vary to 3.6v, the +v ccp1 and +2.5v s /+v ccp1 inputs are internally scaled such that the adc result is 0h for a 0v input and the maximum value of ffh is returned for a voltage of 3.60v. this corresponds to an lsb weighting of 14.1 mv. the inputs can also be used to monitor a negative sup- ply, such as 12v. however, a resistor ladder and posi- tive reference voltage (v ref ) must be used (see figure 1) such that input voltage to the DS1780 swings between ov and +3.6v. assuming the DS1780 +v ccp1 and +2.5v s /+v ccp 2 pins have infinite input impedance and the v ref is a perfect supply, then the resolution and range of 12v input are: lsb r 1 , r 2 3.6 r 1 + r 2 r 1 255 v min v ref , r 1 , r 2 r 2 r 1 v max v ref , r 1 , r 2 v ref v ref 3.6 r 1 + r 2 r 1 v ref if the +2.5v s /+v ccp2 is to be used to monitor a second- ary processor core voltage (v ccp2 ), r2 should be removed and r1=500 w . table 6 below shows the volt- age/data relationship for these inputs in the ideal case. in this example, v ref =+5.0v, r1=4.0k w , and r2=23.2k w .
DS1780 072898 10/28 analog inputs will provide best accuracy when referred to the gnda pin. a separate, lowimpedance ground plane for analog ground, which provides a ground point for the voltage dividers and analog components, will provide best performance, but is not mandatory. analog components such as voltage dividers should be located physically as close as possible to the DS1780. the power supply bypass, the parallel combination of 10 m f (electrolytic or tantalum) and 0.1 m f (ceramic) bypass capacitors connected between pin 9 and ground, should also be located as close as possible to the DS1780. voltage/data relationships for v ccp voltage inputs (+v ccp1 , +2.5vs/ +v ccp2 ) table 6 input pin + v ccp1 + 2.5v s / + v ccp2 lsb weighting (mv) 14.1 96.0 (used to monitor v ccp ) (used to monitor 12v) adc result (base 10) pin voltage (v) supply voltage (v) 0 0 29.0 1 0.014 28.90 2 0.028 28.81 3 0.042 28.71 4 0.056 28.62 136 1.920 15.94 137 1.934 15.85 138 1.948 15.75 139 1.962 15.66 252 3.558 4.808 253 3.572 4.712 254 3.586 4.616 255 3.60 4.52 operation fan speed data format inputs are provided for signals from fans equipped with tachometer outputs. these are logiclevel inputs with an approximate threshold of 1.4v. signal conditioning in the DS1780 accommodates the slow rise and fall times typical of fan tachometer outputs. the maximum input signal range is 0 to v dd . in the event these inputs are supplied from fan outputs which exceed 0 to v dd , either resistive division or diode clamping must be included to keep inputs within an acceptable range, as shown in figure 3. r2 is selected so that it does not develop excessive voltage due to input leakage. r1 is selected based on r2 to provide a minimum input of 2v and a maximum of v dd . r1 should be as low as possible to provide the maximum possible input up to v dd for best noise immunity. alternatively, use a shunt reference or zener diode to clamp the input level. tables 7 and 8 describe the format of the data stored in the fan reading registers (internal address registers 28h and 29h).
DS1780 072898 11/28 fan tachometer input options figure 3 +12v +5v a) fan with tach pullup to +5v fanx input r p 4.7k w +12v b) fan with tach pullup to +12v, totempole output with attenuator fanx input r p 4.7k w +12v c) fan with tach pullup to +12v and diode clamp fanx input r p >1k w r 1 r 2 v z = 3.9v +12v d) fan with tach pullup to +12v, totempole output and diode clamp fanx input r p >1k w v z = 3.9v r1>1k w voltage/data relationships for fan inputs (fan1, fan2) under default ( 2 ) mode table 7 rpm time per revolution counts for `divide by 2' (default mode) in decimal comments 4400 13.64 ms 153 typical rpm 3080 19.48 ms 219 70% rpm 2640 22.73 ms 255 (maximum) 60% rpm voltage/data relationships for fan inputs (fan1, fan 2) table 8 mode select nominal rpm time per revolution counts for the nomi- nal speed in decimal 70% rpm time per revolu- tion for 70% rpm divide by 1 8800 6.82 ms 153 6160 9.74 ms divide by 2 4400 13.64 ms 153 3080 19.48 ms divide by 4 2200 27.27 ms 153 1540 38.96 ms divide by 8 1100 54.54 ms 153 770 77.92 ms in general, the value stored in the fan registers (in deci- mal) follows the equation: count rpm, divisor rpm divisor 1.35 x 10 6 if fans can be powered while the power to the DS1780 is off, the DS1780 inputs will provide diode clamping. limit input current to the input current at any pin specifica- tion shown in the absolute maximum ratings section. in most cases, open collector outputs with pullup resistors inherently limit this current. if this max- imum current could be exceeded, either a larger pullup resistor should be used or resistors connected in series with the fan inputs. the fan inputs gate an internal 22.5 khz oscillator for one period of the fan signal into an 8bit counter (maxi- mum count = 255). the default divisor, located in the fan divisor/rst_ register, is set to 2 (choices are 1, 2, 4, and 8) providing a nominal count of 153 for a 4400 rpm fan with two pulses per revolution. typical practice is to consider 70% of normal rpm a fan failure, at which point the count will be 219.
DS1780 072898 12/28 operation interrupts an external interrupt can come from the following sources. while the label suggests a specific type or source of interrupt, this label is not a restriction on the usage; it could come from any desired source. 1. analog voltage: an interrupt will be generated if a analog voltage high or low limit has been exceeded; this is generally when a power supply is out of its normal operating range. 2. temperature: an interrupt will be generated if a high or a low hot temperature limit has been exceeded. 3. fan speed: an interrupt will be generated if a fan count limit has been exceeded. 4. chassis intrusion: this is an active high interrupt from any type of device that detects and captures chassis intrusion violations. this could be accom- plished mechanically, optically, or electrically, and circuitry external to the DS1780 is expected to latch the event. all system management interrupts (smi's) are indi- cated in the two interrupt status registers. the int out- put has individual mask registers and individual masks for each interrupt. as described in the aoperation configuration registero section, this hardware interrupt line can also be enabled/disabled in the configuration register. reading an interrupt status register will output the con- tents of the register, and reset the register. a subse- quent read done before the analog `roundrobin' moni- toring loop is complete will indicate a cleared register. allow at least 1 second to allow all registers to be updated between reads. in summary, the interrupt sta- tus register clears upon being read, and requires at least 1 second to be updated. when the interrupt status register clears, the hardwire interrupt line will also clear until the registers are updated by the monitoring loop. the int hardware interrupt output is cleared with the int_clear bit, which is bit 3 of the configuration regis- ter, without affecting the contents of the interrupt status registers. when this bit is high, the DS1780 monitoring loop will stop. it will resume when the bit is low. analog voltage limits the limits for the analog voltage comparison are pro- grammed into the value ram at internal address regis- ters 2bh 36h. a high and low limit is associated with each of the 6 analog voltage inputs of the DS1780. care must be taken to program the limit registers in the same format as the respective voltage data register. please see aoperation voltage data formato for details. for setting a voltage interrupt, the DS1780 compares on a agreater thano basis for high limits and a aless than or equal too basis for low limits. the host can mask any or all of the voltage limits for interrupt contention. temperature limits and interrupt modes the host programs an 8bit high temperature limit and hysteresis/low temperature limit into the DS1780 at internal address registers 39h and 3 ah in the same 2's complement format described in the aoperation temperature data formato section. the temperature mode is programmed into the temperature configura- tion register (0x4bh). a digital 8bit comparator is also incorporated that compares the temperature readings to the programmed limits. there are three interrupt modes of operation. the int output can be programmed for either of the three inter- rupt modes of operation and the host can program the DS1780 to completely mask temperature interrupts from controlling the int output. 1. onetime interrupt mode: exceeding hot temper- ature limit causes an smi that will remain active indefinitely until reset by reading interrupt status register 1 or cleared by the int_clear bit in the con- figuration register. once an smi event has occurred by crossing the hot temperature limit, then subse- quently reset, an smi will not occur again until the temperature goes below hot temperature hysteresis (low) limit. 2. default interrupt mode: exceeding hot tempera- ture limit causes an system management interrupt (smi) that will remain active indefinitely until reset by reading interrupt status register 1 or cleared by the int_clear bit in the configuration register. once an interrupt event has occurred by crossing the hot temperature limit, then reset, an interrupt will occur again once the next temperature conversion has completed. the interrupts will continue to occur in this manner until the temperature goes below the hot temperature hysteresis value.
DS1780 072898 13/28 3. comparator mode: exceeding hot temperature limit causes the smi output to go active. smi will remain active until the temperature goes below the hot temperature limit. once the temperature goes below the hot temperature limit, smi will become inactive. as in the default and onetime interrupt modes, the smi can also be cleared by reading interrupt status register 1 or by setting the int_clear bit in the configuration register. figure 4 below illustrates the 3 temperature interrupt modes. fan speed limits the host programs 8bit fan speed low limits for fan1 and fan2 inputs into internal address registers 3bh and 3ch, respectively. care must be taken to program the limit with respect to the divisor chosen for each of the tachometer inputs. refer to the aoperation fan speed data formato section for details. an interrupt will occur if measured fan speed falls below the pro- grammed limit. due to the nature of the algorithm imple- mented, a count of 255 (max) represents a slow (or stopped) fan; i.e., tachometer counts are inversely pro- portional to fan speed. thus, the fan limit register will contain the maximum number of counts (or the mini- mum fan speed) before which an interrupt will occur. chassis intrusion detection the chs input is an active high interrupt from any type of device that detects and captures chassis intrusion violations. this could be accomplished mechanically, optically, or electrically, and circuitry external to the DS1780 is expected to latch the event. the design of the DS1780 allows this input to go high even with no power applied to the DS1780, and no clamping or other interference with the line will occur. this line can also be pulled low for at least 20 ms by the DS1780 to reset a typical chassis intrusion circuit. accomplish this reset by setting bit 6 of configuration register high. the bit in the register is selfclearing. a possible chassis intrusion detector/latch is shown below in figure 5.
DS1780 072898 14/28 temperature interrupt mode illustration figure 4 t high t hyst measured temperature inactive active smi state inactive active smi state inactive active smi state onetime interrupt mode conversions assumes an smi clear occurred conversions default interrupt mode assumes an smi clear occurred conversions comparator mode conversions
DS1780 072898 15/28 sample chassis intrusion detector/latch figure 5 100k w chs input cmos backup battery +5v mm74hc132 470k w 10k w operation analog output the DS1780 has a single analog output from a unsigned 8bit d/a which produces 01.25 volts; this is amplified and scaled with external circuitry such as a opamp and transistor to provide fan speed control. this register is set to 0xff on powerup, which produces full fan speed. the analog output register (19h) is unaffected by any reset other than poweron. this voltage must be scaled and have a output current of at least 250 ma which is needed to drive the fans; fig- ure 6 is a simple circuit that can be used, and table 9 suggest r1 and r2 to select gain. although it is recommended to connect the DS1780 analog output to a high impedance node such as that in figure 6, the output driver can source 2.0 ma (max) at v out = 1.25v while maintaining the error spec of 5% of fsr over temperature and supply voltage. stability is guaranteed for a load capacitance up to 100 pf. more capacitance could cause severe overshoots and pos- sible oscillation. amplifier design examples table 9 input 1.22 output 12 gain 9.84 r1 r2 1,000 9,000 2,200 19,439 3,300 29,159 4,700 41,530 10,000 88,361 operation nand tree test a nand tree is provided in the DS1780 for automated test equipment (ate) board level connectivity testing. if the user applies (v dd 0.5v) to the nt in input, the device will be in the nand tree test mode. a0/nt out will become the nand tree output pin. to perform a nand tree test all pins included in the nand tree (see figure 7 below) should be driven high. fan amplifier circuit example figure 6 +12v r in >1m w v out /nt in r 1 r 2 + beginning with a1 and working around the chip, each pin can be toggled and a resulting toggle can be observed on a0/nt out . allow for a typical propagation delay of 100 ns. note: to properly implement the nand tree test on the pcb, no pins listed in the tree should be connected directly to power or ground; if a pin is needed to config- ure as a permanent low, such as an address, it should be connected to ground through a low value resister such as 330( to allow the ate (automatic test equip- ment) to drive it high.
DS1780 072898 16/28 DS1780 nand tree test flow figure 7 a1 sda fan1 scl fan2 vid0 vid1 vid2 vid3 vid4 nt out DS1780 registers and ram internal address register table 10.0 bit name r/w description <7:0> address pointer w address of ram and registers. see the tables below for detail. address pointer (power on default 00h) table 10.1 registers and ram (hex) power on value of registers: <7:0> (binary) configuration register 40h 0000 1000 interrupt int status register 1 41h 0000 0000 interrupt int status register 2 42h 0000 0000 int mask register 1 43h 0000 0000 int mask register 2 44h 0000 0000 chassis intrusion clear register 46h 0000 0000 vid register 47h <7:4> = 0101, <3:0> = vid3 vid0 serial address register 48h 0010 1101 vid 4 register 49h <7:1> = 1000 000, <0>=vid 4 temperature configuration register 4bh 0000 0001 test register 15h 0000 0000 analog output 19h 1111 1111 value ram 20h3dh company id 3eh 1101 1010 stepping 3fh 0000 0001
DS1780 072898 17/28 configuration register (address 0x40; powerup default = 08h) table 10.2 bit name r/w description 0 start r/w logic 1 enables startup of measurement loop, logic 0 places the DS1780 in standby mode. caution: the int output pin will not be cleared if the user writes a zero to this location after an interrupt has occurred (see aint clearo bit). at startup, limit checking functions and scanning begins. note, all high and low limits should be set into the DS1780 prior to turning on this bit. (powerup default=0). 1 int enable r/w logic 1 enables the int output. 1=enabled 0=disabled (powerup default = 0). 2 reserved r/w powerup default = 0. 3 int clear r/w during interrupt service routine (isr) this bit asserted logic 1 clears int out- put without affecting the contents of the interrupt status registers. the device will stop monitoring. it will resume upon clearing of this bit. (powerup default=1). 4 reset r/w creates a reset (active low) signal for 20 ms (min) on the rst output. (pow- erup default = 0) this bit is cleared once the rst pulse goes active. 5 reserved r/w powerup default = 0. 6 chs reset r/w logic 1 resets the chassis intrusion pin. (powerup default = 0). this bit is cleared after chs becomes cleared. 7 initialization r/w logic 1 restores powerup default values to all DS1780 registers except for the analog output and value ram, which remain unchanged. this bit automatically clears itself since the power on default is zero. interrupt int status register 1 (address 0x41; powerup default = 00h) table 10.3 bit name r/w description 0 +2.5v_error r a one indicates a high or low limit has been exceeded. 1 vccp1_error r a one indicates a high or low limit has been exceeded. 2 +3.3v_error r a one indicates a high or low limit has been exceeded. 3 +5v_error r a one indicates a high or low limit has been exceeded. 4 temp_error r a a1o indicates that a high or low temperature limit has been exceeded. the conditions that will generate and clear this bit depend upon the temperature interrupt mode chosen. the mode is set at bits 0 and 1 of the temperature con- figuration register (0x48h). 5 reserved r a0o. 6 fan1_error r a one indicates that a fan count limit has been exceeded. 7 fan2_error r a one indicates that a fan count limit has been exceeded.
DS1780 072898 18/28 interrupt int status register 2 (address 0x42; powerup default=00h) table 10.4 bit name r/w description 0 +12v_error r a one indicates a high or low limit has been exceeded. 1 12v/ vccp2_error r a one indicates a high or low limit has been exceeded. 2 reserved r a0o. 3 reserved r a0o. 4 chassis_error r a one indicates chassis intrusion has gone high. 5 reserved r a0o. 6 reserved r a0o. 7 reserved r a0o. note: anytime the int status registers are read out, the conditions (i.e., registers) that are read are auto- matically reset to powerup state (except chs, which can only be cleared by chs reset). in the case of the voltage priority indication, if two or more voltages were out of limits, then another indication would auto- matically be generated if it was not handled during the isr. the errant voltage may be masked until the operator has time to clear the errant condition or set the limit high- er/lower. int mask register 1 (address 0x43; powerup default=00h) table 10.5 bit name r/w description 0 +2.5v r/w a one disables the corresponding interrupt status bit for int interrupt. 1 +vccp1 r/w a one disables the corresponding interrupt status bit for int interrupt. 2 +3.3v r/w a one disables the corresponding interrupt status bit for int interrupt. 3 +5v r/w a one disables the corresponding interrupt status bit for int interrupt. 4 temp r/w a one disables the corresponding interrupt status bit for int interrupt. 5 reserved r/w power on default = 0. 6 fan1 r/w a one disables the corresponding interrupt status bit for int interrupt. 7 fan2 r/w a one disables the corresponding interrupt status bit for int interrupt.
DS1780 072898 19/28 int mask register 2 (address 0x44; powerup default=00h) table 10.6 bit name r/w description 0 +12v r/w a one disables the corresponding interrupt status bit for int interrupt. 1 12v/vccp2 r/w a one disables the corresponding interrupt status bit for int interrupt. 2 reserved r/w powerup default = 0. 3 reserved r/w powerup default = 0. 4 chs_sec (chassis intrusion) r/w a one disables the corresponding interrupt status bit for int interrupt. 5 reserved r/w powerup default = 0. 6 reserved r/w powerup default = 0. 7 reset enable r/w a one enables the reset in the configuration register. reserved register (address 0x45; powerup default=00h) table 10.7 bit name r/w description <7:0> reserved r/w undefined (power on = 00h). chassis intrusion clear register (address 0x46; powerup default=00h) table 10.8 bit name r/w description 06 reserved r/w undefined (power on = 00h). 7 chassis int clear r/w a one outputs a minimum 20 ms active low pulse on the chassis intrusion (chs) pin. the register bit clears itself after the pulse has been output. vid register (address 0x47; powerup default = see aaddress pointero table) table 10.9 bit name r/w description 03 vid r the vid[3:0] inputs from pentium/pro power supplies to indicate the operat- ing voltage (e.g., 1.5v to 2.9v). 45 fan1 rpm control r/w fan1 speed control. <5:4> = 00 divide by 1 <5:4> = 01 divide by 2 <5:4> = 10 divide by 4 <5:4> = 11 divide by 8 67 fan2 rpm control r/w fan2 speed control. <7:6> = 00 divide by 1 <7:6> = 01 divide by 2 <7:6> = 10 divide by 4 <7:6> = 11 divide by 8
DS1780 072898 20/28 serial address register (address 0x48; powerup default = see description below) table 10.10 bit name r/w description 07 2wire bus address r/w 2wire bus address (power on = 001011(a1)(a0)). vid4 register (address 0x49; powerup default = see description below table 10.11 bit name r/w description 0 vid 4 r vid4 input. 17 reserved r/w default power on values = 1000000. temperature configuration register (address ox4b; powerup default = 01h) table 10.12 bit name r/w description 0 hot tempera- ture interrupt mode select bit 0 r/w if bits 0 and bits 1 of this register are both zero or both one, this selects the default interrupt mode which gives the user an interrupt if the temperature goes above the hot limit. the interrupt will be cleared once the status register is read, but it will again be generated when the next conversion has completed. it will continue to do so until the temperature goes below the hysteresis limit. a zero on bit 1 and a one on bit 0 selects the one time interrupt mode which gives the user an indefinite interrupt when it goes above the hot limit. the inter- rupt will be cleared once the status register is read. another interrupt will not be generated until the temperature first goes below the hysteresis limit. it will also be cleared if the status register is read. no more interrupts will be gener- ated until the temperature goes above the hot limit again. the corresponding bit will be cleared in the status register every time it is read but may not set again when the next conversion is done. 1 hot tempera- ture interrupt mode select bit 1 r/w a one on this bit (bit 1) and a zero on bit 0 selects the comparator mode. this gives an smi when the temperature exceeds the hot limit. this smi remains active until the status register is read or the temperature goes below the hot limit (no hysteresis), when the smi will become inactive. 26 reserved r/w default = 00000. 7 temp [0] r ninth bit of the temperature (value = 0.5 c). test register (address 0x15h; powerup default = 00h) table 10.13 address h r/w description 15h note 3 powerup default = 00h. analog output (address 0x19h; powerup default = ffh) table 10.14 address h r/w description 19h r/w powerup default = ffh. no other reset affects this register. ffh value set ana- log out to max value = 1.25v.
DS1780 072898 21/28 value ram (address 0x15h 0x3dh) table 10.15 address h r/w description 20h r +2.5v input reading. 21h r vccp1 input reading. 22h r +3.3v input reading. 23h r +5v input reading. 24h r +12v input reading. 25h r +2.5v_sense /vccp2 input reading. 26h r reserved. 27h r temperature reading (most significant 8bits). 28h r fan1 reading: this location stores the number of counts of the internal clock per revolution. 29h r fan2 reading: this location stores the number of counts of the internal clock per revolution. 2ah r/w reserved. 2bh r/w +2.5v high limit (note 1, 2). 2ch r/w +2.5v low limit (note 2). 2dh r/w +vccp1 high limit (note 1, 2). 2eh r/w +vccp1 low limit (note 2). 2fh r/w +3.3v high limit (note 1, 2). 30h r/w +3.3v low limit (note 2). 31h r/w +5v high limit (note 1, 2). 32h r/w +5v low limit (note 2). 33h r/w +12v high limit (note 1, 2). 34h r/w +12v low limit (note 2). 35h r/w +2.5v_sense/vccp2 high limit (note 1, 2). 36h r/w +2.5v_sense/vccp2 low limit (note 2). 37h reserved. 38h reserved. 39h r/w hot temperature (high) limit (note 1). 3ah r/w hot temperature hysteresis (low) limit.
DS1780 072898 22/28 value ram (addresses 0x15h 0x3dh) table 10.13 (cont'd) address h r/w description 3bh r/w fan1 fan count limit: it is the number of counts of the internal clock for the low limit of the fan speed. 3ch r/w fan2 fan count limit: it is the number of counts of the internal clock for the low limit of the fan speed. 3dh reserved. 3eh r company id number (note 5). 3fh r stepping id number (note 6). notes: 1. setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. 2. for the high limits of the voltages, the device is doing a greater than comparison. for the low limits, however, it is doing a less than or equal comparison. 3. this register should only be used by the manufacturer for testing of the asic. reading or writing to this register during normal use may lead to erroneous events. 4. this register will latch an 8bit value into an r2r d/a to provide a range of 01.25 volts, accuracy can be 5% or more. 5. this location will contain the company identification number which will be used by software to determine analog voltage curves, this register is read only. 6. this location will contain the stepping number of the part, this register is read only.
DS1780 072898 23/28 absolute maximum ratings* voltage on v dd (gndd0.3v) to +6.5v voltage on any other pin (except analog inputs) (gndd0.3v) to (v dd + 0.3v) voltage at +12v in pin (gndd0.3v) to 18v voltage at other analog input pins (gndd0.3v) to 7.0v ground difference (gnddgnda) 0.3v input current at any pin (note 2) 5 ma package input current (note 2) 20 ma operating temperature 40 c to +125 c storage temperature 65 c to +150 c esd susceptibility (human body model) 2kv soldering temperature (note 3) 215 c for 60 seconds (vapor phase) 220 c for 15 seconds (ir) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. the dallas semiconductor DS1780 is built to the highest quality standards and manufactured for long term reliability. all dallas semiconductor devices are made using the same quality materials and manufacturing methods. however, the DS1780 is not exposed to environmental stresses, such as burnin, that some industrial applications require. for specific reliability information on this product, please contact the factory in dallas at (972) 3714448. recommended dc operating conditions (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes supply voltage v dd 2.8 5.75 v ground difference d gnd |gnddgnda| 0.1 v digital input voltage v ind 0.05 v dd + 0.05 v dc electrical characteristics power supply (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes slc i active adc and dac, interface inactive 0.7 1.0 ma 45 supply current i dd adc, dac and interface inactive 125 m a 4, 5 inactive adc and interface, dac active 250 500 m a dc electrical characteristics: temperaturetodigital converter (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes thermometer error t err 40 c ta 125 c 3 c 25 c ta 100 c 2 resolution 0.5 c
DS1780 072898 24/28 dc electrical characteristics: voltagetodigital converter (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes adc resolution 8 bits voltage to digital conversion resolution +2.5v in input 13.0 mv conversion resolution (see voltage a/d section) +3.3v in input 17.2 (g ) +5v in input 26.0 +12v in input 62.5 +v ccp1,2 inputs 14.1 +2.5v s input 64.0 total unadjusted error tue 0 c ta 100 c 1.5 % 6 t o t a l u na dj us t e d e rror tue 40 c ta +125 c 2 differential nonlinearity dnl 1 lsb power supply sensitivity pss 1 %/v monitoring cycle t c 0.5 1.0 s 7 input resistance r in 500k 750k w dc electrical characteristics: fan rpmtodigital converter (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes accuracy 0 c ta 100 c 6 % 40 c ta +125 c 12 full scale count 255 decimal fan1 & fan2 nominal input rpm divisor=1; fan count=153 8800 rpm 8 divisor=2; fan count=153 4400 divisor=4; fan count=153 2200 divisor=8; fan count=153 1100 internal oscillator frequency +25 c ta +75 c 21.15 22.5 23.85 khz
DS1780 072898 25/28 dc electrical characteristics: analog output v out (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes dac resolution 8 bits voltage range 0 1.25 v error dac err 5 % of fsr output current i out 2.0 ma load capacitance c load 100 pf dc electrical characteristics: digital outputs: a0nt out (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical a1o output voltage v out (1) i out = 5 ma at v dd =4.25v 2.4 v i out = 3 ma at v dd =2.85v logical a0o output voltage v out (0) i out = 5 ma at v dd =5.75v 0.4 v i out = 3 ma at v dd =3.45v dc electrical characteristics: opendrain digital outputs: rst , chs, int (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical a0o output voltage v out (0) i out = 5 ma at v dd =5.75v 0.4 v i out = 3 ma at v dd =3.45v high level output current i oh v out =v dd 0.1 100 m a active pulse width rst and chs 20 45 ms dc electrical characteristics: opendrain 2wire bus output: sda (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical a0o output voltage v out (0) i out = 5 ma at v dd =5.75v 0.4 v i out = 3 ma at v dd =3.45v high level output current i oh v out =v dd 0.1 100 m a
DS1780 072898 26/28 dc electrical characteristics: 2wire bus digital inputs: sda, scl (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical a1o input voltage v in (1) 0.7v dd v logical a0o input voltage v in (0) 0.3v dd v dc electrical characteristics: digital inputs: a0/nt out , a1, chs, vid04, fan1, fan2 (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical a1o input voltage v in (1) v dd =5.0v 2.4 v logical a0o input voltage v in (0) v dd =5.0v 0.8 v logical a1o input voltage v in (1) v dd =3.3v 2.0 v logical a0o input voltage v in (0) v dd =3.3v 0.4 v dc electrical characteristics: all digital inputs (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical a1o input current i in (1) v in =v dd 1 0.005 m a logical a0o input current i in (0) v in =0v 0.005 1 m a input capacitance c in 20 pf ac electrical characteristics: 2wire interface (40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes scl clock period t 1 2.5 m s data in setup time to scl high t 2 100 ns data out stable after scl low t 3 0 ns sda low setup time to scl low (start) t 4 100 ns sda high hold time after scl high (stop) t 5 100 ns
DS1780 072898 27/28 2wire bus timing diagram figure 8 t 1 scl sda data in sda data out t 2 t 4 t 5 t 3 notes: 1. all voltages are referenced to ground, unless otherwise specified. 2. when the input voltage (vin) at any pin exceeds the power supplies (v in < (gnd or gnda) or v in >v dd , except for analog voltage inputs), the current at that pin should be limited to 5 ma. the 20 ma maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 ma to four. 3. solder according to ipc standards. 4. idd specified with opendrain output pin open. 5. idd specified with vcc at 5.0v and sda,scl = 5.0v. 6. tue (total unadjusted error) includes offset, gain and linearity errors of the adc. 7. monitoring cycle time includes temperature conversion, voltage conversions, an fan speed readings. 8. the total fan count is based on 2 pulses per revolution of the fan tachometer output. 9. limits (min and max specs) are defined for the full temperature range 40 c t a +125 c and voltage range 2.8v v dd 5.75v, unless otherwise stated as a condition. typical values represent parametric norms at t a = 25 c at 4.5v v dd 5.5v, unless otherwise stated as a condition.
DS1780 072898 28/28 DS1780 24 ld. tssop

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